The integration of high value capacitors in integrated circuits is limited by the fact that conventional high value capacitors take up a large areas of on integrated circuit chip, and restrict interconnect routing in the region of the capacitor, thus reducing the device packing density and layout efficiency. Many applications, including telecommunications equipment, require a large number of capacitors, e.g. as coupling/decoupling capacitors and for filters. Often, these must be incorporated as discrete off-chip components, substantially increasing cost, weight, and volume of the peripheral circuitry.
The minimum dimensions of integrated circuit capacitors are determined primarily by the relatively low dielectric constant (e<10), of conventional capacitor dielectrics, e.g. silicon dioxide and silicon nitride. Thus as device dimensions decrease, there is increasing interest in other dielectrics with higher dielectric constants. As discussed in U.S. Pat. No. 5,789,303, ferroelectric materials have large dielectric constants (about 500), and thus they are also ideally suited as dielectrics for fabrication of integrated circuit capacitors with small dimensions and large capacitance values, e.g. for use as coupling/de-coupling capacitors and as filter elements. However, because ferroelectric materials contain chemical elements not typically found in conventional integrated circuit materials, interdiffusion of elements of the ferroelectric material, heavy metals from the electrode materials, and surrounding materials may occur, causing contamination and degradation of electrical characteristics This is of particular concern where ferroelectric materials are in close proximity to active devices.
U.S. Pat. No. 6,287,910 to Lee, et al. on Sep. 11, 2001 shows a method for fabricating a capacitor for a semiconductor device by forming a lower electrode on an understructure of a semiconductor substrate; depositing an amorphous TaON thin film over the lower electrode; subjecting the amorphous TaON thin film to a thermal process in an NH3 atmosphere to form a Ta3N5 dielectric film; and forming an upper electrode on the Ta3N5 dielectric film. In another embodiment, Lee shows a method for fabricating a capacitor for a semiconductor device, comprising the steps of forming a lower electrode on an understructure of a semiconductor substrate; forming an amorphous TaON thin film over the lower electrode; subjecting the amorphous TaON thin film to a thermal process in an NH3 atmosphere at a temperature of 600 to 950 degree C. to form a Ta3N5 dielectric film; annealing the Ta3N5 dielectric film; and forming an upper electrode on the Ta3N5 dielectric film. In another embodiment, Lee provides a method for fabricating a capacitor for a semiconductor device, comprising the steps of forming a lower electrode on an understructure of a semiconductor substrate; nitriding the lower electrode in an NH3 atmosphere; forming an amorphous TaON thin film over the lower electrode; subjecting the amorphous TaON thin film to a thermal process in an NH3 atmosphere at a temperature of 600 to 950 degree C. to form a Ta3N5 dielectric film; annealing the Ta3N5 dielectric film; and forming an upper electrode on the Ta3N5 dielectric film.